There is an increasing trend to integrate more floating-point hardware on the main data processor chip. While on-chip integration of floating-point hardware is desirable, limitations of available chip area on high-performance data processors present implementation obstacles. Although integer and floating point division occur infrequently in data processors, divide operations are difficult to pipeline and typically have long latencies. Consequently, in many data processors a significant performance degradation occurs as a result of such data processor performing a divide operation. Furthermore, most data processing systems employ co-processors to perform faster floating-point division, while the main data processor performs the integer divide operations. Thus, today's data processors are generally characterized by slow divide performance, and specifically by slow integer divide performance. This phenomenon is attributable to the fact that faster floating-point divide performance exists primarily on co-processors, but not on single-chip data processors, and not for integer divide.
Floating-point non-restoring SRT division may have a final remainder equal to the divisor in magnitude, but of an opposite sign. When this occurs, the remainder is actual zero. This negative divisor remainder can result in an incorrect sticky bit, and therefore, incorrect rounding unless the remainder is somehow corrected. Generally, conventional techniques employed to solve this problem slow down the division process. For example, one technique is to add the divisor to any negative remainder at the conclusion of the division process, and to determine whether the result is zero. Accordingly, this technique requires an additional add and logical OR evaluation at the conclusion of the division process. Another technique is to ensure that if the current partial remainder is zero, the division process is not carried further. In SRT division, this technique slows the critical quotient selection speed since additional logic is required to detect the condition where the irredundant upper bits of the partial remainder are zero. In non-restoring division, stopping the division process on a zero partial remainder involves a wired-OR operation after each partial remainder is formed. Thus, conventional techniques generally require an additional back-end cycle or iterative cycle for a negative sticky detection.